- VLSI Design and CAD Research
- Design Automation Tools
- Reconfigurable Computing
- High-Level Synthesis
- Logic Synthesis
- Hardware Description Languages
- “Automated Design Synthesis and Partitioning for Adaptive Reconfigurable Hardware,” R. Vemuri, S. Govindarajan, I. Ouaiss, et al. In Hardware Implementation of Intelligent Systems, Editors H. N. Teodorescu, L. Jain, and A. Kandel, CRC press., 2001.
- “An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures,” I. Ouaiss et al. in Jose Rolim (Ed.), Parallel and Distributed Processing, Lecture Notes in Computer Science, Vol. 1388, pp. 31-36, Springer-Verlag, 1998.
Refereed journal papers:
- “Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations”, G. Zgheib and I. Ouaiss, in Journal of Circuits, Systems, and Computers , World Scientific, Vol. 24, No. 3, March 2015.
- “Optimizing Functional Unit Binding during Simulated Annealing”, L. Bassil and I. Ouaiss, in International Journal of Computers and Applications, ACTA Press, pp. 58-65, Vol. 34, No. 1, 2012.
- “Priority-Driven Area Optimization in High-Level Synthesis”, M. Abi Saad and I. Ouaiss, in the Journal of Circuits, Systems, and Computers, World Scientific, pp. 1131-1163, Vol. 20, No. 6, October 2011.
- “A Novel Register Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis”, E. El Aaraj and I. Ouaiss, in the Journal of Circuits, Systems, and Computers, World Scientific, pp. 943-973, Vol. 20, No. 5, August 2011.
- “6. “Deadline-Based Connection Setup in Wavelength-Routed WDM Networks”, W. Fawaz, I. Ouaiss, K. Chen, and H. Perros, in the International Journal of Computer and Telecommunications Networks, Elsevier, pp. 1792-1804, Vol. 54, Issue 11, August 2010.
- “7. “A Novel Pseudorandom Noise and Band Jammer Generator Using a Composite Sinusoidal Function”, S. Saab, J. Hobeika, and I. Ouaiss, in IEEE Transactions on Signal Processing, pp. 535-543, Vol. 58, No. 2, February 2010.
Refereed proceedings volumes:
- “Optimizing Register Binding in FPGAs Using Simulated Annealing”, A. Avakian and I. Ouaiss, in Proceedings of International Conference on Reconfigurable Computing and FPGAs (ReConFig’05), IEEE Computer Society Press, September 2005.
- “Storage Allocation for Diverse FPGA Memory Specifications”, D. Dagher and I. Ouaiss, in Proceedings of International Conference on Field-Programmable Logic and Applications (FPL’04), pp. 606-616, Springer, August-September 2004.
- “Register Binding for FPGAs with Embedded Memory”, H. Al Atat and I. Ouaiss, Proceedings of Symposium on Field-Programmable Custom Computing (FCCM’04), pp. 167-175, IEEE, April 2004.
- “A Comparative Study of Device Driver APIs Towards a Uniform Linux Approach”, W. Zaatar and I. Ouaiss, Proceedings of the Ottawa Linux Symposium, pp. 407-413, June, 2002.
- “Memory Synthesis for FPGA Based Reconfigurable Computers,” A. Kasat, I. Ouaiss, and R. Vemuri, Proceedings of International Workshop on Field-Programmable Logic and Applications (FPL’01), Springer, August 2001.
- “Global Memory Mapping for FPGA-Based Reconfigurable Systems,” I. Ouaiss and R. Vemuri, Proceedings of the Reconfigurable Architectures Workshop (RAW’01), IEEE Computer Society Press, April 2001.
- “Hierarchical Memory Mapping During Synthesis in FPGA-Based Reconfigurable Computers,” I. Ouaiss and R. Vemuri, Proceedings of Design, Automation and Test in Europe (DATE’01), pp. 650-657, IEEE Computer Society Press, March 2001.
- “Efficient Resource Arbitration in Reconfigurable Computing Environments,” I. Ouaiss and R. Vemuri, Proceedings of Design, Automation and Test in Europe (DATE’00), pp. 560-566, IEEE Computer Society Press, March 2000.
- “An Automated Temporal Partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications,” M. Kaul, R. Vemuri, S. Govindarajan, and I. Ouaiss, IEEE/ACM Design Automation Conference (DAC’99), pp. 616-622, IEEE Computer Society Press, June 1999.
- “An Automated Temporal Partitioning Tool for a class of DSP applications,” M.Kaul, R. Vemuri, S. Govindarajan, and I. Ouaiss, Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT’98) Workshop on Reconfigurable Computing, pp. 22-27, October 1998.
- “A Unified Specification Model of Concurrency and Coordination for Synthesis from VHDL,” I. Ouaiss, et al. Fourth International Conference on Information Systems, Analysis and Synthesis (ISAS’98), Volume 3, pp. 771-778, International Institute of Informatics and Systematics, July 1998.
- “An Effective Design System for Dynamically Reconfigurable Architectures,” S. Govindarajan, I. Ouaiss, et al., Proceedings of Sixth Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’98), pp. 312-313, IEEE Computer Society, April 1998.
- “Instant Learning v/s Iterative Learning in a Flat Neural Network Used in the Localisation of Epileptogenic Foci,” I. Ouaiss and C. L. P. Chen, Proceedings of the World Congress on Neural Networks (WCNN’95), Vol. II, pp. 776-780, Washington, D.C., 1995.
- “Localisation of Epileptogenic Foci Using Artificial Neural Networks,” I. Ouaiss, A. Dhawan, and M. Privitera, Proceedings of the 16th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBS’94), November 1994.
Committee-reviewed proceedings volumes:
- “Partitioning and Synthesis for Run-Time Reconfigurable Computers Using the SPARCS System,” M. Kaul, V. Srinivasan, S. Govindarajan, I. Ouaiss and R. Vemuri, Proceedings of the Conference on Military Applications of Programmable Logic Devices (MAPLD’98), 15 pages, September 1998.
Ph.D., Computer Engineering, University of Cincinnati, USA, 2002
B.S., Computer Engineering, University of Cincinnati, USA, 1994
Office: Bassil 107