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Bee Colony Optimization in High-Level Synthesis

High-Level Synthesis (HLS) is the process of converting an algorithmic description into a digital hardware design; the process can be broken into multiple tasks including scheduling, allocation, and optimization. HLS is an optimization problem where the best design out of multiple other feasible solutions has to be found. Conventional design space exploration algorithms are struggling to keep up with the fast-evolving field of Very Large Scale Integrated Circuits (VLSI). Such NP-hard problems are best solved using heuristics/metaheuristics, and in this paper, a Bee Colony Optimization (BCO) algorithm is proposed as a metaheuristic for the Datapath Synthesis (DS) problem. The implementation optimizes for both design area and design latency by doing resource-restrained and time restrained scheduling. The algorithm also takes into consideration the possibility of multiple Functional Units (FU) each having its delay and area characteristics. The proposed algorithm’s performance is compared to other algorithms such as Simulated Annealing (SA), As Soon As Possible scheduling (ASAP) and As Late As Possible scheduling (ALAP), to properly evaluate the BCO performance in DS. The algorithm mentioned above is tested on well-known benchmarks to evaluate the validity of the proposed solution. In addition, the paper explores the impact of each parameter of the BCO algorithm on the produced solution in order to fine-tune the implementation and produce better results. In addition to the BCO itself, the paper proposes a parallel adaptation of the algorithm based on the CUDA architecture of modern Graphics Processing Unit (GPU). The same benchmarks are used to evaluate the parallel implementation and compare its execution speed to the sequential BCO algorithm.  Report in pdf

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